Semiconductor structure

ABSTRACT

A semiconductor structure includes a semiconductor device, a conductive line, a dielectric layer and a redistribution layer (RDL). The conductive line is present over the semiconductor device. The dielectric layer is present over the conductive line. The RDL includes a conductive structure over the dielectric layer and a conductive via extending downwards from the conductive structure and through the dielectric layer. The conductive via comprises a bottom portion, a top portion, and a tapered portion between the bottom and top portions, wherein the tapered portion has a width variation greater than that of the bottom and top portions.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Divisional Application of the U.S. applicationSer. No. 16/439,690, filed on Jun. 12, 2019, the entirety of which isincorporated by reference herein in their entireties.

BACKGROUND Technical Field

The present disclosure relates to a semiconductor structure. Moreparticularly, the present disclosure relates to a semiconductorstructure including a redistribution layer (RDL).

Description of Related Art

With the rapid growth of electronic industry, the development ofintegrated circuits (ICs) has achieved high performance andminiaturization. Technological advances in IC materials and design haveproduced generations of ICs where each generation has smaller and morecomplex circuits than the previous generation. As a result, via holesfor a redistribution layer (RDL) of an IC are scaled down as well.

SUMMARY

According to some embodiments of the present disclosure, a semiconductorstructure includes a semiconductor device, a conductive line, adielectric layer and a redistribution layer (RDL). The conductive lineis present over the semiconductor device. The dielectric layer ispresent over the conductive line. The RDL includes a conductivestructure over the dielectric layer and a conductive via extendingdownwards from the conductive structure and through the dielectriclayer. The conductive via comprises a bottom portion, a top portion, anda tapered portion between the bottom and top portions, wherein thetapered portion has a width variation greater than that of the bottomand top portions.

According to some embodiments of the present disclosure, the taperedportion tapers from the top portion to the bottom portion.

According to some embodiments of the present disclosure, the bottomportion is in contact with the conductive line.

According to some embodiments of the present disclosure, thesemiconductor structure further includes a protective layer. Theprotective layer is present over the RDL.

According to some embodiments of the present disclosure, the bottomsurface of the conductive via is below the top surface of the conductiveline.

In summary, the disclosure provides a semiconductor structure andfabrication method. The via hole includes the bottom portion, thetapered portion, and the top portion. Since the tapered portion and thetop portion are wider than the bottom portion, the tapered portion andthe top portion can provide more space for metal deposition, which inturn can mitigate any adverse impact resulting from the overhang offollowing metal deposition. Moreover, the bottom portion is more narrowthan the tapered portion and the top portion, in such a way, an improvedvia density can be achieved.

It is to be understood that both the foregoing general description andthe following detailed description are by examples, and are intended toprovide further explanation of the disclosure as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure can be more fully understood by reading the followingdetailed description of the embodiment, with reference made to theaccompanying drawings as follows:

FIG. 1 is a schematic cross-section view showing a semiconductorstructure in accordance with some embodiments of the present disclosure.

FIGS. 2-3 and 5-14 are schematic cross-sectional views of a method offorming a semiconductor structure at various stages in accordance withsome embodiments of the present disclosure.

FIG. 4 is a schematic view of an embodiment of a photomask which is usedto pattern a photoresist layer.

DETAILED DESCRIPTION

Reference will now be made in detail to the present embodiments of thedisclosure, examples of which are illustrated in the accompanyingdrawings. Wherever possible, the same reference numbers are used in thedrawings and the description to refer to the same or like parts.

FIG. 1 is a schematic cross-section view showing a semiconductorstructure 10 in accordance with some embodiments of the presentdisclosure. Referring to FIG. 1, a dielectric layer 300 is present overan interconnect structure 130 that is present over a substrate 110. Aredistribution layer 700 a including a conductive via 710 and aconductive structure 720 a is present over the substrate 110. The RDL700 a is in contact with the dielectric layer 300. A protective layer900 is present over and covers the RDL 700 a.

In some embodiments, the substrate 110 may be a silicon substrate.Alternatively, the substrate 110 may include another elementarysemiconductor, such as germanium; a compound semiconductor includingsilicon carbide, gallium arsenic, gallium phosphide, indium phosphide,indium arsenide, and/or indium antimonide; an alloy semiconductorincluding SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; orcombinations thereof. In yet another alternative, the substrate 110 is asemiconductor-on-insulator (SOI) such as having a buried layer.

In some embodiments, one or more active and/or passive devices 120 areformed over the substrate 110. The one or more active and/or passivedevices 120 may include various N-type metal-oxide semiconductor (NMOS)and/or P-type metal-oxide semiconductor (PMOS) devices, such astransistors, capacitors, resistors, diodes, photo-diodes, fuses, and thelike.

The interconnect structure 130 is formed over the one or more activeand/or passive devices 120 and the substrate 110. The interconnectstructure 130 electrically interconnects the one or more active and/orpassive devices 120 to form functional electrical circuits within thesemiconductor structure 10. The interconnect structure 130 may includeone or more metallization layers 140 ₀ to 140 _(n), wherein n+1 is thenumber of the one or more metallization layers 140 ₀ to 140 _(n). Insome embodiments, the value of n may vary in response to designspecifications of the semiconductor structure 10. The metallizationlayers 140 ₁ to 140 _(n) may include dielectric layers 152 ₁ to 152_(n), conductive plugs 160 ₀, conductive lines 170 ₁ to 170 _(n), andconductive vias 180 ₁ to 180 _(n). The dielectric layers 152 ₁ to 152_(n) are formed over the corresponding dielectric layers 150 ₁ to 150_(n).

In some embodiments, the metallization layer 140 ₀ may includeconductive plugs 160 ₀ through the dielectric layer 150 ₀, and themetallization layers 140 ₁ to 140 _(n) comprise one or more conductiveinterconnects, such as conductive lines 170 ₁ to 170 _(n) respectivelyin dielectric layers 152 ₁ to 152 _(n) and conductive vias 180 ₁ to 180_(n) respectively in dielectric layers 150 ₁ to 150 _(n). The conductiveplugs 160 ₀ electrically couple the one or more active and/or passivedevices 120 to the conductive lines 170 ₁ to 170 _(n) and the conductivevias 180 ₁ to 180 _(n). In some embodiments where a passive device 120is a transistor, the conductive plugs 160 ₀ can be respectively land ona gate electrode, and source/drain regions of the passive device(transistor) 120 and thus respectively serve as a gate contact, andsource/drain contacts.

In some embodiments, the conductive plugs 160 ₀, the conductive lines170 ₁ to 170 _(n) and the conductive vias 180 ₁ to 180 _(n) may beformed using any suitable method, such as damascene, dual damascene, orthe like. The conductive plugs 160 ₀, the conductive lines 170 ₁ to 170_(n) and the conductive vias 180 ₁ to 180 _(n) may comprise conductivematerials such as copper, aluminum, tungsten, combinations thereof, orthe like. In some embodiments, the conductive plugs 160 ₀, theconductive lines 170 ₁ to 170 _(n), and the conductive vias 180 ₁ to 180_(n) may further comprise one or more barrier/adhesion layers (notshown) to protect the respective dielectric layers 150 ₀ to 150 _(n) and152 ₀ to 152 _(n) from metal diffusion and metallic poisoning. The oneor more barrier/adhesion layers may comprise titanium, titanium nitride,tantalum, tantalum nitride, or the like, and may be formed usingphysical vapor deposition (PVD), CVD, ALD, or the like.

FIGS. 2, 3 and 5-14 are schematic cross-sectional views of a method offorming a semiconductor structure 10 at various stages in accordancewith some embodiments of the present disclosure. In order to clearlyillustrate the features in the present embodiment, the substrate 110 andthe interconnect structure 130 (as shown FIG. 1) are not shown in FIGS.2, 3 and 5-14.

Referring to FIG. 2, a dielectric layer 300 is formed over theconductive line 170 _(n). The method of forming the dielectric layer 300may use, for example, PVD, CVD, ALD, or other suitable technique. Insome embodiments, the dielectric layer 300 may include a single ormultiple layers. The dielectric layer 300 may include silicon oxide,silicon nitride, silicon oxynitride, or other suitable materials. Insome embodiments, a barrier layer (not shown) is formed over theconductive line 170 _(n) before the dielectric layer 300 is formed. Thebarrier layer may be beneficial to the adhesion between the conductiveline 170 _(n) and the dielectric layer 300.

Referring to FIG. 3, a photoresist layer 400 is formed over thedielectric layer 300. In some embodiments, the method of forming thephotoresist layer 400 may include forming a plasma enhancedtetraethoxysilane (PETEOS) film over the dielectric layer 300. In someembodiments, the photoresist layer 400 may include an organic material,such as a spin-on carbon (SOC) material, or the like.

Referring to FIG. 4 and FIG. 5, FIG. 4 is a schematic view of aphotomask 410 which is used to pattern a photoresist layer 400 in FIG.3. As shown in FIG. 4, the photomask 410 includes a light transmissiveportion 412, a light semi-transmissive portion 414, and a lightshielding portion 416. The density of light shielding area of the lightshielding portion 416 is larger than that of the light semi-transmissiveportion 414. The light semi-transmissive portion 414 is present betweenthe light transmissive portion 412 and the light shielding portion 416.In some embodiments, the method of forming the photomask 410 with thelight transmissive portion 412, the light semi-transmissive portion 414,and the light shielding portion 416 may use chrome on glass (COG), phaseshift mask, or other suitable methods.

As shown in FIG. 5, the photomask 410 (as shown FIG. 4) is used topattern the photoresist layer 400 (as shown FIG. 3) and thus a maskfeature 420 is formed. In other words, the photoresist layer 400 (asshown FIG. 3) is patterned by using suitable photolithography techniquesto form a mask feature 420. The mask feature 420 has an outer portion422 and an inner portion 424. The inner portion 424 is wider than theouter portion 422. The inner portion 424 is in contact with thedielectric layer 300.

In the present embodiment, an opening 500 is defined by the mask feature420, and the opening 500 exposes the dielectric layer 300. The openinghas a bottom portion 502 and a top portion 504, and the top portion 504is communicated to the bottom portion 502. In greater detail, the bottomportion 502 has a width W1, while the top portion 504 has a width W2.The width W2 is wider than the width W1. Since the light transmissiveportion 412, semi-transmissive portion 414, and the shielding portion416 of the photomask 410 have different light transmission depths, themask feature 420 in FIG. 5 is caused to have the opening 500, and theopening 500 has the bottom portion 502 with the width W1 and the topportion 504 with the width W2.

Referring to FIG. 6, the dielectric layer 300 is etched using the maskfeature 420 as an etch mask. This etching process results in a via hole600 in the dielectric layer 300, and the via hole 600 has substantiallywidth W1 as the width W1 of the bottom portion 502 of the opening 500 inthe mask feature 420, because the etching process is performed using themask feature 420 as an etch mask.

As shown in FIG. 6, a portion of the dielectric layer 300 remains belowthe via hole 600. The via hole 600 is present below the opening 500. Inother words, the portion of the dielectric layer 300 remains between thevia hole 600 and the underlying conductive line 170 _(n).

In some embodiments, the method of etching the dielectric layer 300 mayuse dry etching. The dry etchant, e.g., H₂ and N₂, may be selected fordry etching process to etch the dielectric layer 300.

Referring to FIG. 7, the dielectric layer 300 is etched using the maskfeature 420 as an etch mask such that the via hole 600 is deepened andexpanded. In greater details, the inner portion 424 of the mask feature420 is consumed during the etching process, and thickness of the outerportion 422 of the mask feature 420 is reduced, such that the outerportion 422 of the mask feature 420 is aligned with the inner portion424 of the mask feature 420. In other words, a portion of the dielectriclayer 300 below the inner portion 424 is etched after the inner portion424 of the mask feature 420 is consumed, thereby causing the via hole600 having a tapered profile. Stated differently, since the mask feature420 (as shown FIG. 6) has a stepped profile, e.g., the inner portion 424and the outer portion 422, the via hole 600 has a tapered profile. Insome embodiments, the width of the top portion 504 of the opening 500 isequal to that of the bottom portion 502 of the opening 500. Since themask feature 420 has an laterally expanded bottom portion 502 of theopening 500, the etching process results in laterally expanding the topportion 600 t of the via hole 600 in an interface of the dielectriclayer 300 and the mask feature 420. In greater detail, the top portion600 t of the via hole 600 is expanded and has a width W2. For example,the width W2 of the top portion 600 t of the via hole 600 is equal tothe width W2 of the top portion 504 of the opening 500 in FIG. 5.

In some embodiments, etching the dielectric layer 300 to expand the viahole 600 in FIG. 7 is in-situ performed with the previous etchingprocess in FIG. 6. Stated differently, the etching process of expandingthe via hole 600 and the etching process in FIG. 6 can be performedwithout vacuum break. For example, the etching process of expanding thevia hole 600 and the etching process in FIG. 6 can be performed in thesame etching tool and have substantially the same etching parameters.

Referring to FIG. 8, the dielectric layer 300 is etched using the maskfeature 420 as the etch mask. In greater detail, the etching processdeepens the via hole 600 until reaching the conductive line 170 _(n). Inother words, the conductive line 170 _(n) is exposed. In someembodiments, etching the dielectric layer 300 to deepen the via hole 600in FIG. 8 is in-situ performed with the previous etching process in FIG.7. Stated differently, the etching process of deepening the via hole 600and the etching process of expanding the via hole 600 (as shown in FIG.7) can be performed without vacuum break. For example, the etchingprocess of deepening the via hole 600 and the etching process ofexpanding the via hole 600 can be performed in the same etching tool andhave substantially the same etching parameters.

Referring to FIG. 9, the dielectric layer 300 is etched using the maskfeature 420 as the etch mask. The etching process deepens the via hole600 such that a recess R is formed within the conductive line 170 _(n).In greater detail, the via hole 600 has a bottom portion 602, a taperedportion 604 over the bottom portion 602, and a top portion 606 over thetapered portion 604. The tapered portion 604 tapers from the top portion606 to the bottom portion 602. A width variation of the bottom portion602 is less than that of the tapered portion 604, and a width variationof the top portion 606 is less than that of the tapered portion 604 aswell. The bottom portion 602 of the via hole 600 is in contact with theconductive line 170 _(n). In other words, the bottom portion 602 of thevia hole 600 is in contact with the dielectric layer 300 and theconductive line 170 _(n).

In some embodiments, the width of the bottom portion 602 issubstantially unchanged, and the width of the top portion 606 issubstantially unchanged as well. Since the tapered portion 604 and thetop portion 606 is wider than the bottom portion 602, the taperedportion 604 and the top portion 606 can provide more space for followingmetal deposition, which in turn can mitigate the adverse impactresulting from overhang of following metal deposition. Moreover, becausethe bottom portion 602 is narrower than the tapered portion 604 and thetop portion 606, an improved via density can be achieved.

In some embodiments, deepening the via hole 600 within the conductiveline 170 _(n) is in-situ performed with the previous etching process ofdeepening the via hole 600 in the dielectric layer 300 (as shown in FIG.8). In other words, the etching process of deepening the via hole 600within the conductive line 170 _(n) and the etching process of deepeningthe via hole 600 in the dielectric layer 300 can be performed withoutvacuum break. For example, the etching process of deepening the via hole600 within the conductive line 170 _(n) and the etching process ofdeepening the via hole 600 in the dielectric layer 300 can be performedin the same etching tool and have substantially the same etchingparameters.

Referring to FIG. 10, the mask feature 420 is removed. In someembodiments, removing the mask feature 420 may be performed by using aphotoresist strip process, such as an ashing process.

Referring to FIG. 11, a conductive material is filled in the via hole600. In other words, the conductive material is also filled into therecess R (as shown FIG. 10). As shown in FIG. 11, a conductive layer 700is formed over the dielectric layer 300. In the greater detail, theconductive layer 700 includes a conductive via 710 and a conductivestructure 720. The conductive layer 700 covers the dielectric layer 300and is filled into the via hole 600 to form the conductive via 710 inthe via hole 600. In some embodiments, the conductive layer 700 includesa metal or a metal alloy such as aluminum (Al), copper (Cu), othersuitable conductive material, or combinations thereof. The conductivelayer 700 may be formed by a PVD method such as sputtering method, orother suitable methods.

In the present embodiment, the conductive via 710 extends downwards fromthe conductive structure 720 and through the dielectric layer 300.Because the conductive via 710 fills the via hole 600, the conductivevia 710 inherits the profile of the via hole 600. In greater detail, theconductive via 710 includes a bottom portion 712, a tapered portion 714,and a top portion 716. The tapered portion 714 tapers from the topportion 716 to the bottom portion 712. A width variation of the bottomportion 712 is less than that of the tapered portion 714, and a widthvariation of the top portion 716 is less than that of the taperedportion 714 as well. For example, the width of the bottom portion 712 issubstantially unchanged, and the width of the top portion 716 issubstantially unchanged as well. In the present embodiment, the bottomsurface of the conductive via 710 is below the top surface of theconductive line 170 _(n).

Referring to FIG. 12, a patterned mask feature 800 is formed over theconductive layer 700. The patterned mask feature 800 covers a portion ofthe conductive structure 720, while exposes the other portion of theconductive structure 720. In the present embodiment, the patterned maskfeature 800 is a photoresist layer. The method of forming the patternedmask feature 800 may include first forming a photoresist layer and thenpatterning the photoresist layer with a photolithography process.

Afterwards, the conductive layer 700 is patterned using the patternedmask feature 800 as an etch mask. The resulting structure is shown inFIG. 13. After patterning the conductive layer 700 using suitableetching techniques, the patterned mask feature 800 is removed by, forexample, an ashing process. As shown in FIG. 13, the redistributionlayer (RDL) 700 a includes a conductive structure 720 a and theconductive via 710. The conductive structure 720 a covers the conductivevia 710 and a portion of the dielectric layer 300, while exposes theother portion of the dielectric layer 300.

Referring to FIG. 14, a protective layer 900 is formed on the substrate110 to cover the RDL 700 a and the dielectric layer 300. In someembodiments, the protective layer 900 is a single, double, ormulti-layer structure. The protective layer 900 may include siliconoxide, silicon, silicon oxynitride, silicon nitride, an organicmaterial, a polymer or combinations thereof. The organic material is,for example, benzocyclobutene (BCB), and the polymer is, for example,polyimide (PI). The protective layer 900 may be formed by a CVD method,a coating method, or other suitable method. In the present embodiment,the protective layer 900 includes a silicon oxide layer 910, a siliconnitride layer 920, and a polyimide layer 930.

In summary, the conductive via includes the bottom portion, the taperedportion, and the top portion. Since the tapered portion and the topportion are wider than the bottom portion, the tapered portion and thetop portion are beneficial to mitigating the adverse impact, such asoverhang of metal deposition. Moreover, since the bottom portion is morenarrow than the tapered portion and the top portion, an improved viadensity can be achieved.

Although the present disclosure has been described in considerabledetail with reference to certain embodiments thereof, other embodimentsare possible. Therefore, the spirit and scope of the appended claimsshould not be limited to the description of the embodiments containedherein.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentdisclosure without departing from the scope or spirit of the disclosure.In view of the foregoing, it is intended that the present disclosurecover modifications and variations of this disclosure provided they fallwithin the scope of the following claims.

What is claimed is:
 1. A semiconductor structure, comprising: asemiconductor device; a conductive line over the semiconductor device; adielectric layer over the conductive line; and a redistribution layer(RDL) comprising a conductive structure over the dielectric layer and aconductive via extending downwards from the conductive structure andthrough the dielectric layer, wherein the conductive via comprises abottom portion, a top portion, and a tapered portion between the bottomand top portions, wherein the tapered portion has a width variationgreater than that of the bottom and top portions.
 2. The semiconductorstructure of claim 1, wherein the tapered portion tapers from the topportion to the bottom portion.
 3. The semiconductor structure of claim1, wherein the bottom portion is in contact with the conductive line. 4.The semiconductor structure of claim 1, further comprising: a protectivelayer over the RDL.
 5. The semiconductor structure of claim 1, wherein abottom surface of the conductive via is below a top surface of theconductive line.